1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically to a (split gate type) non-volatile memory device and a method of manufacturing the same.
2. Background of the Related Art
Since some non-volatile memory devices are electrically erasable and programmable and do not require power to retain the programmed data, the scope of their application is being widened increasingly in various fields. Some such non-volatile memory devices (such as flash memory) can be categorized typically into a NAND type and a NOR type. The NAND and NOR memory cells have advantages of high-density integration and high-speed operation, respectively. The NAND or NOR memory devices tend to expand their applications to the fields where the respective advantages are of importance.
In the NOR type non-volatile memory device, a plurality of memory cells is arranged in parallel to a single bit line. Each memory cell is composed of a single transistor. The NOR type non-volatile memory is configured such that a single memory cell transistor is connected between a drain connected to a bit line and a source connected to a common source line. The NOR type memory has an advantage of having a high memory cell current and being capable of being operated at a high speed. However, one drawback thereto is that the bit line contact and the source line occupy a larger relative area of the device, which can present challenges for high-density integration.
A NOR type non-volatile memory device may be configured such that its memory cells are connected in parallel to a bit line. Thus, if a threshold voltage of the memory cell transistor is lower than a voltage (commonly 0V) applied to the wordline of an unselected memory cell, current may flow between the source and the drain regardless of ‘on’ or ‘off’ state of a selected memory cell. In such a case, the device may malfunction (i.e., the memory cell may be read as having an ‘on’ state). In order to solve this problem, a non-volatile memory device having a split gate architecture (or split gate type) has been proposed.
A non-volatile memory device such as a flash memory device may have a layered configuration such as a FLOTOX structure or a SONOS structure, having a multi-layered gate insulation film and a structure similar to a MOS transistor. In the case of SONOS devices, the gate insulation film comprises a multi-layered charge storage insulation layer, and charge is stored in a deep level (or oxide-nitride interface) trap. In some cases, the SONOS structure may provide better reliability, as compared with a flash memory device, and enable program and erase operations at a lower voltage.
A conventional method of manufacturing a split gate type non-volatile memory device is shown in FIGS. 1 to 3.
Referring to FIG. 1, a device isolation film (not shown) is formed in or on a semiconductor substrate 10 to define an active region 11, and then a charge storage layer, a first conductive film and a capping film are formed. In case of a SONOS device where an insulation film having a high trap density is between a tunnel insulation film and a blocking insulation film to form the charge storage layer, in general, a layered silicon oxide film-silicon nitride film-silicon oxide film (ONO film) structure is employed. Further, in the case of a FLOTOX device, which has a layered gate structure including a floating gate, the charge storage layer may be composed of a tunnel oxide film, a polysilicon floating gate and an ONO film. In addition, a buffer layer of silicon oxide and a hard mask layer of silicon nitride may be laminated to form the capping film.
The capping film, first conductive film and charge storage layer are patterned in sequence to form a first conductive film pattern 16 on the active region with a multi-layered charge storage layer 14 interposed in-between, and a capping film pattern where an oxide film pattern 18 and a nitride film pattern 20 are laminated on the first conductive film pattern 16.
Referring to FIG. 2, a lateral insulation film 22 is formed on the side wall of the first conductive film pattern 16, and a gate insulation film 24 is formed on the active region. A second conductive film 26 is formed on the gate insulation film 24 in a conformal manner. At this time, the second conductive film 26 forms a groove G between the first conductive patterns 16 such that it has a side wall. In addition, a photoresist pattern 28 is formed on the second conductive film 26.
As shown in FIG. 3, using the photoresist pattern 28 as an etching mask, the second conductive film 26 is patterned such that the active region between neighboring first conductive patterns 16 can be exposed. The second conductive film 26 is removed through an anisotropic etching process. When the anisotropic etching is being carried out, often polymers or other by-products form (e.g., are stacked) on the side wall portion of the second conductive film 26 between the neighboring first conductive patterns 16 (see FIG. 2) to thereby inhibit the etching process from being smoothly performed. As the result, when the gate insulation film 24 is exposed through etching of the second conductive film 26, a conductive stringer 30 may be formed on the substrate 10. If the over-etching time is extended to completely remove the conductive stringer 30, the substrate 10 may be damaged. In the case where the conductive stringer 30 remains on the substrate, formation of silicide on the surface of the substrate 10 is inhibited, thereby increasing the resistance of the active region 11. Also, the conductive stringer 30 may act as a barrier to formation of a contact pattern, which may increase the contact resistance. Furthermore, the conductive stringers 30 may act as a particle source in subsequent processes.